Split gate non-volatile memory devices are well known in the art. For example, U.S. Pat. No. 7,927,994 discloses a split gate non-volatile memory cell. Currently, it is known to form non-volatile flash memory cells on the same chip as other logic devices, such as low voltage logic devices (core devices) and higher voltage logic devices (HV devices). It is also known to make the memory cell gates and/or the gates of the logic devices of a high K metal material (HKMG—a high K dielectric layer underneath a metal layer). However, separate masking and processing steps are typically used to separately form the memory cells, the core devices and the HV devices, and the process steps for forming devices in one area of the substrate can adversely affect the devices formed in other areas of the substrate.
The present invention is a technique for forming a split gate non-volatile memory device on the same chip as logic devices to minimize the mutual impact and be compatible between flash memory and logic/HV devices.